1. Field of the Invention
The present subject matter relates to an apparatus and a method SEFIs from occurring in an ionizing radiation environment, e.g., outer space, in a processor having a real time operating system.
2. Background
Computers which operate in an ionizing-radiation environment, e.g., outer space, are exposed to ionizing radiation. When gamma rays hit processors, they in effect produce transient signals causing an error in processing behavior. The most significant error events are SEUs (single event upsets) and SEFIs, (single event functional interrupts).
SEUs are defined by NASA as “radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a pathway of electron-hole pairs. SEUs are “soft errors.” In other words, after a processor is reset, normal behavior will follow. However, data may have been corrupted, and the error must be accounted for.
An SEFI is a condition in which a processor's control circuitry causes the processor to cease normal operation. The average number of gamma rays hitting a processor in space has been calculated. The statistical likelihood of causing errors in the process is low. However, such errors must be accounted for and corrected.
U.S. Pat. No. 7,734,970 discloses self-resetting, self-correcting latches in which a value is loaded into at least three latched stages and which senses whether the latched stage outputs are equal. This apparatus may be utilized in a dual core processor or a single core processor. However, this system is not oriented toward responding to SEUs and SEFIs.
United States Patent Publication No. 2008/0082893 discloses error correction in a system for multithreaded computing utilizing dynamic multi-threading redundancy. This system does not provide for time redundant and space redundant error correction.
Prior fault tolerant arrangements do not use multicore processors and have only a single thread of processor operations. United States Patent Publication No. 2009/0031317 discloses an arrangement for scheduling threads in a multi-core system in which threads with fixed affinity for each core are held. This publication does not disclose a fault tolerant system.
Commonly assigned U.S. Pat. No. 7,318,169 discloses a fault tolerant computer including a microprocessor, a fault-tolerant software routine for sending first, second, and third identical instructions to a very long instruction word (VLIW) microprocessor. The instructions are transmitted during first, second, and third clock cycles. If the first and second instructions do not match, a software instruction commands a comparator to compare first, second, and third instructions. Any pair of matching instructions is accepted by the processor as correct.
This construction has been highly successful in solving SEU and SEFI problems. However, this arrangement was provided in the context of a VLIW DSP (very long instruction word digital signal processor). A VLIW DSP utilizes a single instruction stream that issues successive groups of instructions. The VLIW DSP is not suited for running multiple software threads, and the redundancy routine may not be run simultaneously on separate threads.